Jameco-electronics Rabbit 3000 Manuel d'utilisateur Page 1

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User’s Manual 11. INTRODUCTIONRabbit Semiconductor was formed expressly to design a a better microprocessor for use in small and medium-scale control

User’s Manual 917.7 Time/Date Clock (Real-Time Clock)The time/date clock (RTC) is a 48-bit (ripple) counter that is driven by the 32.768 kHz oscillat

92 Rabbit 3000 MicroprocessorTable 7-10. Real-Time Clock RTCxR Data RegistersReal-Time Clock x Holding Register (RTC0R) R/W (Address = 0x02)(RTC1R) (

User’s Manual 937.8 Watchdog TimerThe watchdog timer is a 17-bit counter. In normal operation it is driven by the 32.768 kHz clock. When the watchdog

94 Rabbit 3000 MicroprocessorThe code to do this may also hit the watchdog with a 0.25-second period to speed up the reset. Such watchdog code must be

User’s Manual 957.9 System ResetThe Rabbit 3000 contains a master reset input (pin 46), which initializes everything in the device except for the Rea

96 Rabbit 3000 MicroprocessorTable 7-14. Rabbit 3000 Reset Sequence and State of I/O PinsPin Name Direction/RESET Low* Recognized by CPUPost-Reset†/R

User’s Manual 977.10 Rabbit Interrupt StructureAn interrupt causes a call to be executed, pushing the PC on the stack and starting to exe-cute code a

98 Rabbit 3000 MicroprocessorIn the case of the external interrupts the only action that will clear the interrupt request is for the interrupt to take

User’s Manual 997.10.1 External InterruptsThere are two external interrupts. Each interrupt has 2 input pins that can be used to trig-ger the interru

100 Rabbit 3000 Microprocessor7.10.2 Interrupt Vectors: INT0 - EIR,0x00/INT1 - EIR,0x08When it is desired to expand the number of interrupts for addi

2 Rabbit 3000 Microprocessor1.1 Features and Specifications Rabbit 3000• 128-pin LQFP package. Operating voltage 1.8 V to 3.6 V. Clock speed to 54+ M

User’s Manual 1017.11 Bootstrap OperationThe device provides the option of bootstrap from any of three sources: from the Slave Port, from Serial Port

102 Rabbit 3000 MicroprocessorSerial Port A is selected for bootstrap operation as a clocked serial port when SMODE = 10. In this case bit 7 of Parall

User’s Manual 1037.12 Pulse Width ModulatorThe Pulse Width Modulator consists of a ten-bit free running counter, and four width reg-isters. Each PWM

104 Rabbit 3000 MicroprocessorTable 7-17. PWM LSB x RegisterPWM LSB x Register (PWL0R) (Address = 0x88)(PWL1R) (Address = 0x8A)(PWL2R) (Address = 0x8

User’s Manual 1057.13 Input CaptureThe two-channel Input Capture can be used to time input signals from various port pins. Each Input Capture channel

106 Rabbit 3000 MicroprocessorEach Input Capture counter operates in one of three modes, or can be disabled. The counter is never automatically reset,

User’s Manual 107Table 7-19. Input Capture Control/Status RegisterInput Capture Control/Status Register (ICCSR) (Address = 0x56)Bit(s) Value Descript

108 Rabbit 3000 MicroprocessorTable 7-20. Input Capture Control RegisterInput Capture Control Register (ICCR) (Address = 0x57)Bit(s) Value Descriptio

User’s Manual 109Table 7-22. Input Capture Source x RegisterInput Capture Source x Register (ICS1R) (Address = 0x59)(ICS2R) (Address = 0x5D)Bit(s) Va

110 Rabbit 3000 Microprocessor7.14 Quadrature DecoderThe two-channel Quadrature Decoder accepts inputs, via Port F, from two external optical increme

User’s Manual 3A Rabbit that is slaved to a master processor can operate entirely with volatile RAM, depending on the master for a cold program boot.•

User’s Manual 111The Quadrature Decoder generates an interrupt when the counter increments from 0xFF to 0x00 or when the counter decrements from 0x00

112 Rabbit 3000 MicroprocessorTable 7-25. Quadrature Decoder Control/Status RegisterQuad Decode Control/Status Register (QDCSR) (Address = 0x90)Bit(s

User’s Manual 113Table 7-26. Quadrature Decoder Control RegisterQuad Decode Control Register (QDCR) (Address = 0x91)Bit(s) Value Description7:600Disa

114 Rabbit 3000 Microprocessor

User’s Manual 1158. MEMORY INTERFACE AND MAPPING8.1 Interface for Static Memory ChipsStatic memory chips generally have address lines, data line, a

116 Rabbit 3000 MicroprocessorFigure 8-2. Typical Memory Chip ConnectionRabbit 3000DATA LINES (8)ADDRESS LINES (20) /CS/WE/OE/CS0/CS1/CS2/OE0/OE1/WE0

User’s Manual 1178.2 Memory Mapping OverviewSee Section 3.2, “Memory Mapping,” for a discussion of Rabbit memory mapping.Figure 8-3 shows an overview

118 Rabbit 3000 MicroprocessorFigure 8-4. Memory SegmentsThe memory management unit accepts a 16-bit address from the processor and translates it int

User’s Manual 1198.4 Memory Interface UnitThe 20-bit memory addresses generated by the memory-mapping unit feed into the mem-ory interface unit. The

120 Rabbit 3000 Microprocessor8.5 Memory Bank Control RegistersTable 8-3 describes the operation of the four memory bank control registers. The regis

4 Rabbit 3000 Microprocessor• A built-in clock doubler allows ½-frequency crystals to be used.• The built-in main clock oscillator uses an external cr

User’s Manual 121Bit 3—Inhibits the write pulse to memory accessed in this quadrant. Useful for protecting flash mem-ory from an inadvertent write pul

122 Rabbit 3000 MicroprocessorThe Memory Timing Control Register (MTCR) enables the extended timing for the memory output enables and write enables.

User’s Manual 123The Breakpoint/Debug controller allows the RST 28 instruction to be used as a software breakpoint. Normally the RST 28 instruction ca

124 Rabbit 3000 Microprocessor8.7 Instruction and Data Space SupportInstruction and Data space (I and D space) support is accomplished by optionally

User’s Manual 125are mapped into contiguous regions of memory to create a continuous root code segment starting at the bottom of physical memory in fl

126 Rabbit 3000 MicroprocessorFigure 8-6. Use of Physical Memory Separate I & D Space ModelIn Figure 8-6 arrows indicate the direction in which v

User’s Manual 1278.8 How the Compiler Compiles to MemoryThe compiler actually generates code for root code and constants and extended code and extend

128 Rabbit 3000 Microprocessor

User’s Manual 1299. PARALLEL PORTSThe Rabbit has seven 8-bit parallel ports designated A, B, C, D, E, F, and G. The pins used for the parallel ports

130 Rabbit 3000 Microprocessor9.1 Parallel Port AParallel Port A has a single read/write register:This register should not be used if the slave port

User’s Manual 5Figure 1-1. Rabbit 3000 Block DiagramCPUExternal InterfaceDataBufferMemoryManagement/ControlAddressBufferMemory ChipInterfaceParallel

User’s Manual 1319.2 Parallel Port BParallel Port B, has eight pins that can programmed individually to be inputs and outputs. After reset, Parallel

132 Rabbit 3000 Microprocessor9.3 Parallel Port CParallel Port C, shown in Table 9-6, has four inputs and four outputs. The even-numbered ports, PC0,

User’s Manual 1339.4 Parallel Port DParallel Port D, shown in Figure 9-1, has eight pins that can be programmed individually to be inputs or outputs.

134 Rabbit 3000 MicroprocessorFigure 9-1. Parallel Port D Block DiagramPD7PD4I/O Dataperclk/2Timer A1Timer B1Timer B2perclk/2Timer A1Timer B1Timer B2

User’s Manual 135Table 9-8. Parallel Port D Register functionsBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0PDDR (R/W)adr = 0x060PD7 PD6 PD5 PD4 PD3

136 Rabbit 3000 MicroprocessorThe following registers are described in Table 9-8 and in Table 9-9.• PDDR—Parallel Port D data register. Read/Write.• P

User’s Manual 1379.5 Parallel Port EParallel Port E, shown in Figure 9-2, has eight I/O pins that can be individually pro-grammed as inputs or output

138 Rabbit 3000 MicroprocessorThe following registers are described in Table 9-11 and in Table 9-12.• PEDR—Port E data register. Reads value at pins.

User’s Manual 139Table 9-11. Parallel Port E Register functionsBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0PEDR (R/W)adr = 0x070PE7 PE6 PE5 PE4 PE

140 Rabbit 3000 Microprocessor9.6 Parallel Port FParallel Port F is a byte-wide port with each bit programmable for data direction and drive. These a

6 Rabbit 3000 Microprocessor1.2 Summary of Rabbit 3000 Advantages• The glueless architecture makes it is easy to design the hardware system.• There a

User’s Manual 141The following registers are described in Table 9-14 and in Table 9-15.• PFDR—Port F data register. Reads value at pins. Writes to por

142 Rabbit 3000 MicroprocessorThe functionality of the Parallel Port F pins is not affected for pulse width modulation out-puts and serial clock outpu

User’s Manual 1439.7 Parallel Port GParallel Port G is a byte-wide port with each bit programmable for data direction and drive. These are simple inp

144 Rabbit 3000 MicroprocessorThe following registers are described in Table 9-17 and in Table 9-18.• PGDR—Port G data register. Reads value at pins.

User’s Manual 14510. I/O BANK CONTROL REGISTERSThe pins of Port E can be set individually to be I/O strobes. Each of the eight possible I/O strobes h

146 Rabbit 3000 MicroprocessorTable 10-1 shows how the eight I/O bank control registers are organized.Table 10-1. I/O Bank x Control RegisterI/O Bank

User’s Manual 147The eight I/O bank control registers determine the number of I/O wait states applied to an external I/O access within the zone contro

148 Rabbit 3000 Microprocessor

User’s Manual 14911. TIMERSThere are two timers—Timer A and Timer B. Timer A is intended mainly for generating the clock for various peripherals, bau

150 Rabbit 3000 Microprocessor11.1 Timer ATimer A consists of ten separate countdown timers A1–A10 as shown in Figure 11-1.Timers A1 and A2–A10 are

User’s Manual 71.3 Differences Rabbit 3000 vs. Rabbit 2000For the benefit of readers who are familiar with the Rabbit 2000 microprocessor the Rab-bit

User’s Manual 151For seven of the counters (A1–A7), the terminal count condition is reported in a status regis-ter and can be programmed to generate a

152 Rabbit 3000 MicroprocessorThe following table summarizes Timer A’s capabilities.The control/status register for Timer A (TACSR) is laid out as sho

User’s Manual 1534(write)0 A4 interrupt disabled.1 A4 interrupt enabled.3(read)0 A3 counter has not reached its terminal count.1 A3 count done. This s

154 Rabbit 3000 MicroprocessorThe control register (TACR) is laid out as shown in Table 11-4.The Timer A Prescale Register (TAPR) specifies the main c

User’s Manual 155The time constant register for each timer (TATxR) is simply an 8-bit data register holding a number between 0 and 255. This time cons

156 Rabbit 3000 Microprocessor11.2 Timer BFigure 11-1 shows a block diagram of Timer B. The Timer B counter can be driven directly by perclk/2, by th

User’s Manual 157The control/status register for Timer B (TBCSR) is laid out as shown in Table 11-7.The control register for Timer B (TBCR) is laid ou

158 Rabbit 3000 MicroprocessorThe MSB x registers for Timer B (TBM1R/TBM2R) are laid out as shown in Table 11-9.The LSB x registers for Timer B (TBL1R

User’s Manual 15911.2.1 Using Timer BNormally the prescaler is set to divide perclk/2 by a number that provides a counting rate appropriate to the pr

160 Rabbit 3000 MicroprocessorTimer B can be used for various purposes. The 10-bit counter can be read to record the time at which an event takes plac

8 Rabbit 3000 MicroprocessorSerial ports with support for SDLC/HDLC IrDA communications2NoneMaximum asynchronous baud rate clock speed/8 clock speed/3

User’s Manual 16112. RABBIT SERIAL PORTSThe Rabbit 3000 has 6 on-chip serial ports designated A, B, C, D, E, and F. All the ports can per-form async

162 Rabbit 3000 MicroprocessorFigure 12-1 shows a block diagram of the serial ports.Figure 12-1. Block Diagram of Rabbit Serial PortsSerial Port F TX

User’s Manual 163The individual serial ports are capable of operating at baud rates in excess of 500,000 bps in the asynchronous mode, and 8 times fas

164 Rabbit 3000 Microprocessor12.1 Serial Port Register LayoutFigure 12-2 shows a functional block diagram of a serial port. Each serial port has a d

User’s Manual 165The clock input to the serial port unit must be 8 or 16 (selectable) times the baud rate in the asynchronous mode and 2 times the bau

166 Rabbit 3000 Microprocessor12.2 Serial Port RegistersEach serial port has 6 registers shown in the tables below. The status, control and extended

User’s Manual 167Table 12-5. Serial Port D RegistersRegister Name Mnemonic I/O Address R/W ResetSerial Port D Data Register SDDR 0xF0 R/W xxxxxxxxSer

168 Rabbit 3000 MicroprocessorTable 12-8. Data Register All PortsSerial Port x Data Register (SADR) (Address = 0xC0)(SBDR) (Address = 0xD0)(SCDR) (Ad

User’s Manual 169Table 12-10. Long Stop Register All PortsSerial Port x Long Stop Register (SALR) (Address = 0xC2)(SBLR) (Address = 0xD2)(SCLR) (Addr

170 Rabbit 3000 MicroprocessorTable 12-11. Status Register Asynchronous Mode Only (All Ports)Serial Port x Status Register (SASR) (Address = 0xC3)(SB

User’s Manual 92. RABBIT 3000 DESIGN FEATURESThe Rabbit 3000 is an evolutionary design. The processor and instruction set are nearly identical to the

User’s Manual 171Table 12-12. Status Register Clocked Serial (Ports A-D only)Serial Port x Status Register (SASR) (Address = 0xC3)(SBSR) (Address =

172 Rabbit 3000 MicroprocessorTable 12-13. Status Register HDLC Mode (Ports E and F only)Serial Port x Status Register (SESR) (Address = 0xCB)(SFSR)

User’s Manual 173Table 12-14. Serial Port Control Register Ports A and BSerial Port x Control Register (SACR) (Address = 0xC4)(SBCR) (Address = 0xD4

174 Rabbit 3000 MicroprocessorTable 12-15. Serial Port Control Register Ports C and DSerial Port x Control Register (SCCR) (Address = 0xE4)(SDCR) (A

User’s Manual 175Table 12-16. Serial Port Control Register Ports E and FSerial Port x Control Register (SECR) (Address = 0xCC)(SFCR) (Address = 0xDC)

176 Rabbit 3000 MicroprocessorTable 12-17. Extended Register Asynchronous Mode All PortsSerial Port x Extended Register (SAER) (Address = 0xC5)(SBER)

User’s Manual 177Table 12-18. Extended Register Clocked Serial Mode (Ports A-D only)Serial Port x Extended Register (SAER) (Address = 0xC5)(SBER) (Ad

178 Rabbit 3000 MicroprocessorTable 12-19. Extended Register HDLC Mode (Ports E and F only)Serial Port x Extended Register (SEER) (Address = 0xCD)(SF

User’s Manual 17912.3 Serial Port InterruptA common interrupt vector is used for the receive and transmit interrupts. There is a sepa-rate interrupt

180 Rabbit 3000 Microprocessor12.4 Transmit Serial Data TimingOn transmit, if the interrupts are enabled, an interrupt is requested when the transmit

10 Rabbit 3000 Microprocessor2.1 The Rabbit 8-bit Processor vs. Other ProcessorsThe Rabbit 3000 processor has been designed with the objective of cre

User’s Manual 18112.5 Receive Serial Data TimingWhen the receiver is ready to receive data, a falling edge indicates that a start bit must be detecte

182 Rabbit 3000 Microprocessor12.6 Clocked Serial PortsPorts A–D can operate in clocked mode. The data line and clock line are driven as shown in Fig

User’s Manual 183with new incoming data. Similarly, writing the data to the SxAR register causes the trans-mitter to start a byte transmit operation,

184 Rabbit 3000 Microprocessoranswer its interrupts within 20 µs. There will be no slow down if the receiver can answer its interrupt within 1/2 cloc

User’s Manual 18512.7 Clocked Serial Timing12.7.1 Clocked Serial Timing With Internal ClockFor synchronous serial communication, the serial clock ca

186 Rabbit 3000 MicroprocessorFigure 12-8 shows the timing relationship among perclk, the external serial clock, and data receive. Note that RxA is sa

User’s Manual 18712.8 Synchronous Communications on Ports E and FSerial Port E and F are a dual-function serial ports that can be used in either asyn

188 Rabbit 3000 Microprocessorthe current receive frame is not needed (because it is addressed to a different station, for example) a Flag Search comm

User’s Manual 189In HDLC mode the internal clock comes from the output of Timer A2. This timer output is divided by sixteen to form the transmit clock

190 Rabbit 3000 Microprocessorclock rate must be very small, and depends on the longest possible run of zeros in the received frame. NRZI encoding gua

Rabbit 3000® MicroprocessorUser’s Manual019–0108 • 040731–O®

User’s Manual 11The Rabbit is an 8-bit processor with an 8-bit external data bus and an 8-bit internal data bus. Because the Rabbit makes the most of

User’s Manual 191With NRZ and NRZI encoding all transitions occur on bit-cell boundaries and the data should be sampled in the middle of the bit cell.

192 Rabbit 3000 Microprocessor12.9 Serial Port Software SuggestionsThe receiver and transmitter share the same interrupt vector, but it is possible t

User’s Manual 193LD (HL),A ; 6 update the in pointerIOI LD A,(SCDR) ; 11 get data register port C, clears interrupt requestIPRES ; 4 res

194 Rabbit 3000 Microprocessor2. Clear bit 4 of the Parallel Port C function register so that the output no longer comes from the serial port. Of cou

User’s Manual 195Figure 12-9 illustrates the standard asynchronous serial output patterns.Figure 12-9. Asynchronous Serial Output Patterns12.9.6 Par

196 Rabbit 3000 Microprocessor12.9.8 Supporting 9th Bit Communication ProtocolsThis section describes how 9th bit communication protocols work. 9th b

User’s Manual 197the receiving interrupt service routine to detect this gap, it is suggested that dummy char-acters be transmitted to help detect the

198 Rabbit 3000 Microprocessor

User’s Manual 19913. RABBIT SLAVE PORTWhen a Rabbit microprocessor is configured as a slave, Parallel Port A and certain other data lines are used as

200 Rabbit 3000 MicroprocessorA status register can be read by either the slave or the master. The status register has full/ empty bits for each of th

12 Rabbit 3000 Microprocessorimportant for RS-485 communication because a half duplex line driver cannot have the direction of transmission reversed u

User’s Manual 201The following table explains the parameters used in Figure 13-2.The two SPD0R registers have special functionality not shared by the

202 Rabbit 3000 MicroprocessorFigure 13-3. Slave Port Handshaking and InterruptsFigure 13-4 shows a sample connection of two slave Rabbits to a maste

User’s Manual 203Figure 13-4. Typical Connection Slave Rabbit to Master RabbitThe slave port lines are shown in Figure 13-1. The function of these li

204 Rabbit 3000 Microprocessor• /SLAVEATTN—This line is set low (asserted) if the slave writes to the SPD0R register. This line is set high if the mas

User’s Manual 205If the user for some reason wants to depart from the suggested protocols and poll a register while waiting for the other side to writ

206 Rabbit 3000 MicroprocessorBits 1,0—This 2-bit field sets the priority of the slave port interrupt. The interrupt is disabled by (0,0).Table 13-3 d

User’s Manual 207require a speciality processor. The slave processor can process data to perform pattern recognition or to extract a specific paramete

208 Rabbit 3000 Microprocessorfor this.) Once the software is loaded into the slave, the slave can begin to perform its function.As a simple example,

User’s Manual 20914. RABBIT 3000 CLOCKSThe Rabbit 3000 normally uses two clocks, the main clock and the 32.768 kHz clock. The 32.768 kHz clock is ne

210 Rabbit 3000 Microprocessor14.1 Low-Power DesignThe power consumption is proportional to the clock frequency and to the square of the operating vo

User’s Manual 132.2.5 Parallel I/O There are 56 parallel input/output lines divided among seven 8-bit ports designated A through G. Most of the port

User’s Manual 21115. EMI CONTROLEMI or electromagnetic interference from unintentional radiation is of concern to the microprocessor system designer.

212 Rabbit 3000 Microprocessor15.1 Power Supply Connections and Board LayoutRefer to Technical Note TN221, PC Board Layout Suggestions for the Rabbit

User’s Manual 213When the spectrum spreader is engaged, the frequency is modulated, and individual clock cycles may be shortened or lengthened by an a

214 Rabbit 3000 Microprocessorso low as to be undetectable, except perhaps for extremely weak stations. The effect of a pure harmonic on TV reception

User’s Manual 21516. AC TIMING SPECIFICATIONSThe Rabbit 3000 processor may be operated at voltages between 1.8 V and 3.6 V, and at temperatures from

216 Rabbit 3000 MicroprocessorFigure 16-1 illustrates the parameters used to describe memory access time.Figure 16-1. Parameters Used to Describe Mem

User’s Manual 217Figure 16-2 and Figure 16-3 illustrate the memory read and write cycles. The Rabbit 3000 operates at 2 clocks per bus cycle plus any

218 Rabbit 3000 MicroprocessorThe following memory read time delays were measured.The measurements were taken at the 50% points under the following co

User’s Manual 219Figure 16-3. Memory Read and Write Cycles—EarlyOutput Enable and Write Enable TimingTadrTadrMemory Read (no wait states)CLKA[19:0]Me

220 Rabbit 3000 MicroprocessorFigure 16-4 illustrates the sources that create memory access time delays.Figure 16-4. Sources of Memory Access Time De

14 Rabbit 3000 Microprocessor2.2.6 Slave Port The slave port is designed to allow the Rabbit to be a slave to another processor, which could be anoth

User’s Manual 221The required memory output enable access time is more complicated since it is affected by the clock doubler delays. The clock doubler

222 Rabbit 3000 MicroprocessorThe following factors have to be taken into account when calculating the output enable access time required.• The gross

User’s Manual 22316.2 I/O Access TimeFigure 16-6 illustrates the I/O read and write cycles.Figure 16-6. I/O Read and Write Cycles—No Extra Wait Sta

224 Rabbit 3000 MicroprocessorThe following I/O read time delays were measured.The measurements were taken at the 50% points under the following condi

User’s Manual 22516.3 Further Discussion of Bus and Clock TimingThe clock doubler is normally used, except in situations where low-frequency systems

226 Rabbit 3000 MicroprocessorFigure 16-7. Clock Doubler and Memory TimingOscillatorOscillator delayedand invertedDoubled clockDelaytime48% 52%P0.48P

User’s Manual 22716.4 Maximum Clock SpeedsThe Rabbit 3000 is rated for a minimum clock period of 17 ns (commercial specifications) and 18 ns (industr

228 Rabbit 3000 MicroprocessorExampleThe spreader and doubler are enabled, with 8 ns nominal delay in the doubler. The high and low clock are equal to

User’s Manual 22916.5 Power and Current ConsumptionWith the Rabbit 3000 it is possible to design systems that perform their task with very low power

230 Rabbit 3000 MicroprocessorFigure 16-9. Rabbit 3000 System Current vs. Frequency at 3.3 VFigure 16-10. Rabbit 3000 System Current vs. Frequency a

User’s Manual 152.2.7 Auxiliary I/O BusThe Rabbit 3000 instruction set supports memory access and I/O access. Memory access takes place in a 1 megaby

User’s Manual 231Lowering the operating voltage will greatly reduce current consumption and power. Drop-ping to 2.7 V from 3.3 V will result in 70% cu

232 Rabbit 3000 Microprocessor16.6 Current Consumption MechanismsThe following mechanisms contribute to the current consumption of the Rabbit 3000 wh

User’s Manual 23316.7 Sleepy Mode Current ConsumptionIn sleepy mode the unit operates from the 32.768 kHz clock, which may be divided down to as slow

234 Rabbit 3000 Microprocessor16.8 Memory Current ConsumptionSince there are many different memories available, let’s look at an example using one of

User’s Manual 23516.9 Battery-Backed Clock Current ConsumptionWhen using the suggested tiny logic oscillator, the oscillator and clock consume curren

236 Rabbit 3000 Microprocessor16.10 Reduced-Power External Main OscillatorThe circuit in Figure 16-13 can be used to generate the main clock using le

User’s Manual 23717. RABBIT BIOS AND VIRTUAL DRIVERWhen a program is compiled by Dynamic C for a Rabbit target, the Virtual Driver is auto-matically

238 Rabbit 3000 Microprocessor17.1.2 BIOS AssumptionsThe BIOS makes certain assumptions concerning the physical configuration of the proces-sor. Proc

User’s Manual 239gram consistency checking or because a part of the program that should be executing peri-odically is not executing and the watchdog t

240 Rabbit 3000 Microprocessor

16 Rabbit 3000 MicroprocessorFigure 2-4. Rabbit Timers A and B2.2.9 Input Capture ChannelsThe input capture channels are used to determine the time

User’s Manual 24118. OTHER RABBIT SOFTWARE18.1 Power Management SupportThe power consumption and speed of operation can be throttled up and down wit

242 Rabbit 3000 Microprocessor18.2 Reading and Writing I/O RegistersThe Rabbit has two I/O spaces: internal I/O registers and external I/O registers.

User’s Manual 24318.3 Shadow RegistersMany of the registers of the Rabbit’s internal I/O devices are write-only. This saves gates on the chip, making

244 Rabbit 3000 Microprocessorld hl,PDDDRShadow ; point to shadow registerld de,PDDDR ; set de to point to I/O regset 5,(hl) ; s

User’s Manual 245Two library functions are provided to read and write the real-time clock:unsigned long int read_rtc(void) ; // read bits 15-46

246 Rabbit 3000 Microprocessor

User’s Manual 24719. RABBIT INSTRUCTIONSSummary“Load Immediate Data” on page 250“Load & Store to Immediate Address” on page 250“8-bit Indexed Loa

248 Rabbit 3000 MicroprocessorSpreadsheet ConventionsALTD (“A” Column) Symbol KeyIOI and IOE (“I” Column) Symbol KeyFlag Register KeyFlag Descriptionf

User’s Manual 249SymbolsRabbit Z180 Meaningb bBit select:000 = bit 0, 001 = bit 1,010 = bit 2, 011 = bit 3, 100 = bit 4, 101 = bit 5, 110 = bit 6, 111

250 Rabbit 3000 Microprocessor19.1 Load Immediate DataInstruction clk A I S Z V C OperationLD IX,mn 8 - - - - IX = mnLD IY,mn

User’s Manual 17and stop condition, for example a rising edge could be the start condition and a falling edge the stop condition. However, optionally,

User’s Manual 25119.5 16-bit Load and Store 20-bit AddressInstruction clk A I S Z V C OperationLDP (HL),HL 12 - - - - (HL) = L; (HL+

252 Rabbit 3000 Microprocessor19.7 Exchange InstructionsInstruction clk A I S Z V C OperationEX (SP),HL 15 r - - - - H <-> (SP+

User’s Manual 253ADD IY,yy 4 f - - - * IY = IY + yy -- yy=BC, DE, IY, SPADD SP,d 4 f - - -

254 Rabbit 3000 MicroprocessorCP* n 4 f * * V * A - nCP* r 2 f * * V * A - rOR (HL) 5 fr s * * L 0 A = A |

User’s Manual 25519.13 8-bit Fast A Register OperationsInstruction clk A I S Z V C OperationCPL 2 r - - - - A = ~ANEG

256 Rabbit 3000 MicroprocessorSLA r 4 fr * * L * r = {r[6,0],0}; CY = r[7]SRA (HL) 10 f b * * L * (HL) = {(HL)[7],(HL)[7,1]};

User’s Manual 25719.17 Control Instructions - Jumps and CallsInstruction clk A I S Z V C OperationCALL mn 12 - - - - (SP-1) = PC

258 Rabbit 3000 Microprocessor19.19 Privileged InstructionsThe privileged instructions are described in this section. Privilege means that an interru

User’s Manual 25920. DIFFERENCES RABBIT VS. Z80/Z180INSTRUCTIONSThe Rabbit is highly code compatible with the Z80 and Z180, and it is easy to port no

260 Rabbit 3000 MicroprocessorThe following instructions use different register names.LD A,EIRLD EIR,A ; was R registerLD IIR,ALD A,IIR ; was I

18 Rabbit 3000 Microprocessorlength of the pulses. When the duty cycle is greater then 1/1024 the pulses are spread into groups distributed 256 counts

User’s Manual 26121. INSTRUCTIONS IN ALPHABETICAL ORDERWITH BINARY ENCODINGSpreadsheet ConventionsALTD (“A” Column) Symbol KeyFlag Descriptionf ALTD

262 Rabbit 3000 MicroprocessorSymbolsRabbit Z180 MeaningbbBit select:000 = bit 0, 001 = bit 1,010 = bit 2, 011 = bit 3, 100 = bit 4, 101 = bit 5, 1

User’s Manual 263Instruction Byte 1 Byte 2 Byte 3 Byte 4 clk A I S Z V CADC A,(HL) 10001110 5 fr s

264 Rabbit 3000 MicroprocessorEX AF,AF' 00001000 2 - - - -EX DE,HL 11101011

User’s Manual 265LD A,(BC) 00001010 6 r s - - - -LD A,(DE) 00011010 6 r s

266 Rabbit 3000 MicroprocessorLDP HL,(HL) 11101101 01101100 10 - - - -LDP HL,(IX) 11011101 01101100

User’s Manual 267RR r 11001011 00011-r- 4 fr * * L *RRA 00011111 2 fr

268 Rabbit 3000 Microprocessor

User’s Manual 269APPENDIX A.THE RABBIT PROGRAMMING PORTThe programming port provides a standard physical and electrical interface between a Rabbit-bas

270 Rabbit 3000 MicroprocessorA.1 Use of the Programming Port as a Diagnostic/Setup PortThe programming port, which is already in place, can serve as

User’s Manual 19reset pin, and to a programmable output pin that is used to signal the PC that attention is needed. With proper precautions in design

User’s Manual 271an asynchronous signal suitable for the PC. Since the target controls the clock for both send and receive, the data transmission pro

272 Rabbit 3000 MicroprocessorTable A-1. Preliminary Crystal Frequencies, Memory Access Times, and Baud Rates Crystal Frequency (MHz)Doubled Frequenc

User’s Manual 273APPENDIX B. RABBIT 3000 REVISIONSSince its release, the Rabbit 3000 microprocessor has gone through one revision. The revi-sion refle

274 Rabbit 3000 Microprocessor2. First revision (Rabbit 3000A)—Available in two packages and identified by IL2T for the LQFP package and IZ2T for the

User’s Manual 275(l) The quadrature decoder hardware can be configured to use a 10-bit counter in place of the existing 8-bit counter.(m)An option was

276 Rabbit 3000 MicroprocessorB.1 Discussion of Fixes and ImprovementsTable B-1 lists the bug fixes, improvements, and additions for the various revi

User’s Manual 277B.1.1 Rabbit Internal I/O RegistersTable B-2 summarizes the reset state of the new I/O registers added in the Rabbit 3000A revision.

278 Rabbit 3000 MicroprocessorExternal Interrupt User Enable Register IUER 0x0398 W 00000000Timer A User Enable Register TAUER 0x03A0 W 00000000Timer

User’s Manual 279Table B-3. Reset State of I/O Registers Modified in Rabbit 3000ARegister Name MnemonicI/O AddressR/WRabbit 3000 ResetRabbit 3000A Re

280 Rabbit 3000 MicroprocessorB.1.2 Peripheral and ISR AddressTable B-4. Rabbit 3000 I/O Address Rangesand Interrupt Service VectorsOn-Chip Peripher

20 Rabbit 3000 Microprocessor

User’s Manual 281SYSCALL instruction n/a {IIR[7:1], 0, 0x60}RST 38 instruction n/a {IIR[7:1], 0, 0x70}Secondary Watchdog 0x000C {IIR[7:1], 0, 0x10}Sta

282 Rabbit 3000 MicroprocessorB.1.3 Revision-Level ID RegisterTwo read-only registers are provided to allow software to identify the Rabbit microproc

User’s Manual 283B.1.4 System/User ModeBy default, all of the hardware is accessible by the programmer. However, if a control bit in the Enable Dual

284 Rabbit 3000 MicroprocessorB.1.5 Memory ProtectionThe ability to inhibit writes to physical memory was added. The sixteen 64 KB physical memory bl

User’s Manual 285Table B-7. Write Protect Low RegisterWrite Protect Low Register (WPLR) (Address = 0x0460)Bit(s) Value Description70 Disable 64K wri

286 Rabbit 3000 MicroprocessorTable B-8. Write Protect High RegisterWrite Protect High Register (WPHR) (Address = 0x0461)Bit(s) Value Description70

User’s Manual 287Table B-10. Write Protect Segment x Low RegisterWrite Protect Segment x Low Register (WPSALR) (Address = 0x0481)(WPSBLR) (Address =

288 Rabbit 3000 MicroprocessorTable B-11. Write Protect Segment x High RegisterWrite Protect Segment x High Register (WPSAHR) (Address = 0x0482)(WPS

User’s Manual 289B.1.6 Stack ProtectionStack overflow and underflow can now be detected. Low and high stack limits can be set on 256-byte boundaries.

290 Rabbit 3000 MicroprocessorThe stack protection registers are listed in Table B-12, Table B-13, and Table B-14.Table B-12. Stack Limit Control Reg

Rabbit 3000 MicroprocessorRabbit Semiconductor2932 Spafford StreetDavis, California 95616-6800USATelephone: (530) 757-8400Fax: (530) 757-8402www.rabbi

User’s Manual 213. DETAILS ON RABBITMICROPROCESSOR FEATURES3.1 Processor RegistersThe Rabbit’s registers are nearly identical to those of the Z180 o

User’s Manual 291B.1.7 RAM Segment RelocationNormally when instruction/data separation is enabled, instructions are stored in flash memory and data a

292 Rabbit 3000 MicroprocessorB.1.8 Secondary Watchdog TimerThe secondary watchdog timer (SWDT) is an eight-bit modulo n + 1 counter clocked by the 3

User’s Manual 293B.1.9 New OpcodesEight new opcodes were added to the Rabbit 3000A. UMA and UMS allow multiply-and-add and multiply-and-subtract oper

294 Rabbit 3000 MicroprocessorB.1.9.2 New Block Copy OpcodesThe LDxR family of block move opcodes has been expanded. In the Rabbit 3000 proces-sor, b

User’s Manual 295B.1.10 Expanded I/O Memory AddressingIn the Rabbit 3000, only the lower 8 bits of an I/O address were decoded. To provide room for n

296 Rabbit 3000 MicroprocessorB.1.11 External I/O ImprovementsThree new features have been added to the external I/O strobes: the ability to invert t

User’s Manual 297B.1.12 Short Chip Select Timing for WritesThe Rabbit 3000 provided the ability to produce shorter chip select strobes for reads when

298 Rabbit 3000 MicroprocessorB.1.12.1 Clock Select and Power Save ModesTable B-24 outlines the power save modes available in the Rabbit 3000A. The G

User’s Manual 299B.1.12.2 Short Chip Select TimingWhen short chip selects are enabled for read cycles, the chip select signals are active only for th

300 Rabbit 3000 MicroprocessorFigure B-4. Short Chip Select Timing: CLK/6, Read OperationFigure B-5. Short Chip Select Timing: CLK/4, Read Operation

22 Rabbit 3000 MicroprocessorThe Rabbit (and the Z80/Z180) processor has two accumulators—the A register serves as an 8-bit accumulator for 8-bit oper

User’s Manual 301Figure B-6. Short Chip Select Timing: CLK/2, Read Operationoscillator ADDR DATA T1 T2 Valid /OEx /CSx clock divide-by-2 mode

302 Rabbit 3000 MicroprocessorWhen operating from the 32 kHz oscillator, the same options are available, but the timing is somewhat different. This is

User’s Manual 303Figure B-9. Short Chip Select Timing: 8 kHz, Read OperationFigure B-10. Short Chip Select Timing: 16 kHz, Read Operation32 kHz ADDR

304 Rabbit 3000 MicroprocessorFigure B-11. Short Chip Select Timing: 32 kHz, Read Operation32 kHz ADDR DATA T1 T2 Valid /OEx /CSx clock 32 kHz opera

User’s Manual 305In the case of write cycles, the chip select signals are active only around the trailing edge of the write signal. Wait states are in

306 Rabbit 3000 MicroprocessorFigure B-13. Short Chip Select Timing: CLK/6, Write OperationFigure B-14. Short Chip Select Timing: CLK/4, Write Opera

User’s Manual 307Figure B-15. Short Chip Select Timing: CLK/2, Write Operationoscillator ADDR DATA T1 TWA Valid /WEx /CSx clock divide-by-2 modeT2

308 Rabbit 3000 MicroprocessorThe timing diagrams below illustrate the actual timing for the 32KHz cases of write cycles. In these cases the chip sele

User’s Manual 309Figure B-18. Short Chip Select Timing: 8 kHz, Write OperationFigure B-19. Short Chip Select Timing: 16 kHz, Write Operation32 kHz A

310 Rabbit 3000 MicroprocessorFigure B-20. Short Chip Select Timing: 32 kHz, Write Operation32 kHz ADDR DATA T1 TWA Valid /WEx /CSx clock 32 kHz ope

User’s Manual 233.2 Memory MappingAlthough the Rabbit memory mapping scheme is fairly complex, the user rarely needs to worry about it because the de

User’s Manual 311B.1.13 Pulse Width Modulator ImprovementsSeveral new features have been added to the pulse width modulator. First, a new PWM interru

312 Rabbit 3000 MicroprocessorTable B-25. PWM LSB 0 RegisterPWM LSB 0 Register (PWL0R) (Address = 0x0088)Bit(s) Value Description7:6 write The least

User’s Manual 313Table B-27. PWM LSB 2 and 3 RegistersPWM LSB x Register (PWL2R) (Address = 0x008C)(PWL3R) (Address = 0x008E)Bit(s) Value Descriptio

314 Rabbit 3000 MicroprocessorB.1.14 Quadrature Decoder ImprovementsThe quadrature decoder counters can now be expanded to 10 bits instead of 8 bits.

User’s Manual 315Figure B-22. Quadrature Decode, 8-bit and 10-bit Counter TimingCnt (8 bit) Interrupt I input Q input 00 01 02 03 04 05 06 07

316 Rabbit 3000 MicroprocessorB.2 Pins with Alternate FunctionsThe Rabbit 3000A provides greater flexibility for multiplexing I/O functions to other

User’s Manual 317APPENDIX C. SYSTEM/USER MODEThe Rabbit 3000A is the first Rabbit microprocessor to incorporate a “system/user mode.” The purpose of t

318 Rabbit 3000 MicroprocessorC.1 System/User Mode OpcodesSeven new opcodes have been added to support the System/User mode, and are listed in Table

User’s Manual 319C.2 System/User Mode RegistersTable C-3 lists the new I/O registers added to support the System/User mode.The Enable Dual Mode Regis

320 Rabbit 3000 MicroprocessorThe I/O banks on Port E (enabled for the User mode by IBUER) have a slightly different operation in the User mode. Disab

24 Rabbit 3000 MicroprocessorFigure 3-3. Example of Memory Mapping OperationThe names given to the segments in the figure are evocative of the common

User’s Manual 321C.3 InterruptsWhen enabled for User mode access, a peripheral interrupt (if it is capable of generating an interrupt) can only be re

322 Rabbit 3000 MicroprocessorC.3.1 Peripheral Interrupt PrioritizationMost interrupts can be programmed to occur at any of three priority levels, bu

User’s Manual 323Table C-5. Interrupts—Priority and Action to Clear RequestsPriority Interrupt Source Action required to clear the interruptHighest S

324 Rabbit 3000 MicroprocessorC.4 Using the System/User ModeThe System/User mode is designed to work with new features in the Rabbit 3000A (memory pr

User’s Manual 325C.4.2 Mixed System/User Mode OperationThis mode is similar to the previous mode, but with some portions of the program written for t

326 Rabbit 3000 MicroprocessorC.4.3 Complete Operating SystemThis section describes a “full” use of the System/User mode—separating all common functi

User’s Manual 327APPENDIX D.RABBIT 3000A INTERNAL I/O REGISTERSTable D-1 provides a list of all the Rabbit 3000A internal I/O registers.Table D-1. Ra

328 Rabbit 3000 MicroprocessorMemory Bank 0 Control Register MB0CR 0x0014 W 00001000Memory Bank 1 Control Register MB1CR 0x0015 W xxxxxxxxMemory Bank

User’s Manual 329I/O Bank User Enable Register IBUER 0x0380 W 00000000PWM User Enable Register PWUER 0x0388 W 00000000Quad Decode User Enable Register

330 Rabbit 3000 MicroprocessorPort D Bit 2 Register PDB2R 0x006A W xxxxxxxxPort D Bit 3 Register PDB3R 0x006B W xxxxxxxxPort D Bit 4 Register PDB4R 0x

User’s Manual 25the root segment or it may contain data variables. The stack segment is normally 4K long and it holds the system stack. The XPC segmen

User’s Manual 331I/O Bank 2 Control Register IB2CR 0x0082 W 00000000I/O Bank 3 Control Register IB3CR 0x0083 W 00000000I/O Bank 4 Control Register IB4

332 Rabbit 3000 MicroprocessorInterrupt 0 Control Register I0CR 0x0098 W xx000000Interrupt 1 Control Register I1CR 0x0099 W xx000000Timer A Control/St

User’s Manual 333Serial Port B Address Register SBAR 0x00D1 W xxxxxxxxSerial Port B Long Stop Register SBLR 0x00D2 W xxxxxxxxSerial Port B Status Regi

334 Rabbit 3000 Microprocessor

User’s Manual 335NOTICE TO USERSRABBIT SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COM-PONENTS IN LIFE-SUPPORT DEVICES OR SYSTEMS UN

User’s Manual 337INDEXNumerics5 V tolerant inputs ... 11Aassembly languageinstructions ... 40, 41, 42, 43reading/writing to I/O regis

338 Rabbit 3000 MicroprocessorMmemoryA16, A19 inversions (/CS1 enable) ...121access time ...215access time d

User’s Manual 339PDDDR ... 133PDDR ... 133, 135PDFR ... 133PEBxR ...

340 Rabbit 3000 MicroprocessorSsecondary watchdog timer ..292serial ports ...11, 1619th bit protocols ...196address reg

26 Rabbit 3000 Microprocessor3.2.1 Extended Code SpaceA crucial element of the Rabbit memory mapping scheme is the ability to execute pro-grams conta

User’s Manual 27than the XPC segment, can call other code in the root using short jumps and calls. Code in the XPC segment can also call code in the r

28 Rabbit 3000 Microprocessorfetching an instruction from memory and fetching or storing data in memory. When enabled separate I and D space make avai

User’s Manual 29not have split I and D space and memory accesses to these segments do not distinguish between I and D space.The advantage of having mo

30 Rabbit 3000 MicroprocessorFigure 3-7. Schemes for Data Memory WindowsA third approach is to place the data and root code in RAM in the root segmen

User’s ManualTABLE OF CONTENTSChapter 1. Introduction 11.1 Features and Specifications Rabbit 3000...

User’s Manual 31ded applications. Some applications may require large data arrays or tables that will require additional data memory. For this purpose

32 Rabbit 3000 Microprocessor3.3 Instruction Set Outline“Load Immediate Data to a Register” on page 33“Load or Store Data from or to a Constant Addre

User’s Manual 33• Input/output instructions are now accomplished by normal memory access instructions prefixed by an op code byte to indicate access t

34 Rabbit 3000 Microprocessor3.3.3 Load or Store Data Using an Index RegisterAn index register is a 16-bit register, usually IX, IY, SP or HL, that i

User’s Manual 353.3.4 Register-to-Register MoveAny of the 8-bit registers, A, B, C, D, E, H, and L, can be moved to any other 8-bit regis-ter, for ex

36 Rabbit 3000 Microprocessor3.3.6 Push and Pop InstructionsThere are instructions to push and pop the 16-bit registers AF, HL, DC, BC, IX, and IY. T

User’s Manual 37The BOOL instruction is a special instruction designed to help test the HL register. BOOL sets HL to the value 1 if HL is non zero, ot

38 Rabbit 3000 MicroprocessorThe SBC instruction can also be used to perform a sign extension. ; extend sign of l to HLLD A,lrla ; sign

User’s Manual 393.3.8 Input/Output InstructionsThe Rabbit uses an entirely different scheme for accessing input/output devices. Any memory access ins

40 Rabbit 3000 Microprocessor3.4 How to Do It in Assembly Language—Tips and Tricks3.4.1 Zero HL in 4 ClocksBOOL HL ; 2 clocks, clears carry, HL is

Rabbit 3000 Microprocessor3.5 Interrupt Structure ...

User’s Manual 413.4.4 Comparisons of IntegersUnsigned integers may be compared by testing the zero and carry flags after a subtract operation. The ze

42 Rabbit 3000 MicroprocessorSome simplifications are possible if one of the unsigned numbers being compared is a constant. Note that the carry has a

User’s Manual 43A>B (!S & !V & !Z) v (S & V)A<B (S & !V) v (!S & V & !Z)A==BA>=BA<=BAnother method of doing

44 Rabbit 3000 Microprocessor3.5 Interrupt StructureWhen an interrupt occurs on the Rabbit, the return address is pushed on the stack, and con-trol i

User’s Manual 45the same priority, this introduces interrupt latency while the next routine is waiting for the previous routine to allow more interrup

46 Rabbit 3000 Microprocessor3.5.2 Multiple External Interrupting DevicesThe Rabbit 3000 has two distinct external interrupt request lines. If there

User’s Manual 47The privileged instructions to manipulate the IP register are listed below.IPSET 0 ; shift IP left and set priority 00 in bits 1,0IP

48 Rabbit 3000 Microprocessor3.5.6 Computed Long Calls and JumpsThe instruction to set the XPC is privileged to so that a computed long call or jump

User’s Manual 494. RABBIT CAPABILITIESThis chapter describes the various capabilities of the Rabbit thatmay not be obvious from the technical descrip

50 Rabbit 2000 MicroprocessorPulse width modulated outputs—The minimum pulse width is 10 µs. If the repetition rate is 10 ms, then a new pulse with 10

User’s Manual8.5 Memory Bank Control Registers ...

User’s Manual 514.2 Open-Drain Outputs Used for Key ScanThe Parallel Port D outputs can be individually programmed to be open drain. This is use-ful

52 Rabbit 2000 Microprocessor4.3 Cold BootMost microprocessors start executing at a fixed address, often address zero, after a reset or power-on cond

User’s Manual 534.4 The Slave PortThe slave port allows a Rabbit to act as a slave to another processor, which can also be a Rabbit. The slave has to

54 Rabbit 2000 MicroprocessorOf the three registers seen by each side for each direction of communication, the first reg-ister, slave register zero, h

User’s Manual 555. PIN ASSIGNMENTS AND FUNCTIONS

56 Rabbit 3000 Microprocessor5.1 LQFP Package5.1.1 PinoutRabbit 3000 (AT56C55-IL1T, IL2T)128-pin Low-Profile Quad Flat Pack (LQFP)14 × 14 Body, 0.4

User’s Manual 575.1.2 Mechanical Dimensions and Land PatternFigure 5-2 shows the mechanical dimensions of the Rabbit 3000 LQFP package.Figure 5-2. M

58 Rabbit 3000 MicroprocessorFigure 5-3 shows the PC board land pattern for the Rabbit 3000 chip in a 128-pin LQFP package. This land pattern is based

User’s Manual 595.2 Ball Grid Array Package5.2.1 PinoutRabbit 3000 (AT56C55-IZ1T, IZ2T)128-pin Thin Map Ball Grid Array (TFBGA)10 × 10 Body, 0.8 mm

60 Rabbit 3000 Microprocessor5.2.2 Mechanical Dimensions and Land PatternThe design considerations in Table 5-3 are based on 5 mil design rules and a

Rabbit 3000 MicroprocessorChapter 14. Rabbit 3000 Clocks 20914.1 Low-Power Design...

User’s Manual 61Figure 5-5. BGA Package OutlineABCDEFGHJKLM121110987654321ABCDEFGHJKLM1211109876543210.8010.00 ± 0.050.8010.00 ± 0.050.20~0.301.20(ma

62 Rabbit 3000 Microprocessor5.3 Rabbit Pin DescriptionsTable 5-1 lists all the pins on the device, along with their direction, function, and pin num

User’s Manual 63I/O ports PA[7:0] Input / Output I/O Port A 111–104D7, A8, B8, C8, D8, A9, B9, C9I/O ports (continued) PB[7:0] Input / Output I/O Port

64 Rabbit 3000 Microprocessor5.4 Bus TimingThe external bus has essentially the same timing for memory cycles or I/O cycles. A mem-ory cycle begins w

User’s Manual 655.5 Description of Pins with Alternate FunctionsTable 5-2. Pins With Alternate FunctionsPin Name Output Function Input Function Inpu

66 Rabbit 3000 MicroprocessorPF7 PWM3 AQD2A yesPF6 PWM2 AQD2BPF5 PWM1 AQD1A yesPF4 PWM0 AQD1BPF3 QD2A yesPF2 QD2BPF1 CLKC QD1A, CLKC yesPF0 CLKD QD1B,

User’s Manual 67The alternate output functions identified in Table 5-2 are configured by setting the appro-priate bits in the Paralle Port x Function

68 Rabbit 3000 Microprocessor5.6 DC CharacteristicsStresses beyond those listed in Table 5-5 may cause permanent damage. The ratings are stress ratin

User’s Manual 695.7 I/O Buffer Sourcing and Sinking LimitUnless otherwise specified, the Rabbit I/O buffers are capable of sourcing and sinking 6.8 m

70 Rabbit 3000 Microprocessor

User’s Manual19.16 Block Move Instructions...

User’s Manual 716. RABBIT INTERNAL I/O REGISTERS

72 Rabbit 3000 MicroprocessorTable 6-1. Rabbit 3000 Peripherals and Interrupt Service VectorsOn-Chip Peripheral ISR Starting AddressSystem Management

User’s Manual 736.1 Default Values for all the Peripheral Control RegistersThe default values for all of the peripheral control registers are shown i

74 Rabbit 3000 MicroprocessorGlobal Revision Register GREV 0x2F R 0xx00000Port A Data Register PADR 0x30 R/W xxxxxxxxPort B Data Register PBDR 0x40 R/

User’s Manual 75Port E Bit 7 Register PEB7R 0x7F W xxxxxxxxPort F Data Register PFDR 0x38 R/W xxxxxxxxPort F Control Register PFCR 0x3C W xx00xx00Port

76 Rabbit 3000 MicroprocessorPWM MSB 0 Register PWM0R 0x89 W xxxxxxxxPWM LSB 1 Register PWL1R 0x8A W xxxxxxxxPWM MSB 1 Register PWM1R 0x8B W xxxxxxxxP

User’s Manual 77Timer A Time Constant 5 Register TAT5R 0xAB W xxxxxxxxTimer A Time Constant 6 Register TAT6R 0xAD W xxxxxxxxTimer A Time Constant 7 Re

78 Rabbit 3000 MicroprocessorSerial Port D Address Register SDAR 0xF1 R/W xxxxxxxxSerial Port D Long Stop Register SDLR 0xF2 R/W xxxxxxxxSerial Port D

User’s Manual 797. MISCELLANEOUS FUNCTIONS7.1 Processor IdentificationFour read-only registers are provided to allow software to identify the Rabbit

80 Rabbit 3000 Microprocessor7.2 Rabbit Oscillators and ClocksThe Rabbit 3000 usually requires two separate clocks. The main clock normally drives th

Rabbit 3000 Microprocessor

User’s Manual 8132.768 kHz ClockThe 32.768 kHz clock is primarily used to clock the on-chip real-time clock. In addition, it is also used to support r

82 Rabbit 3000 MicroprocessorTable 7-5. Global Control/Status RegisterGlobal Control/Status Register (GCSR) (Address = 0x00)Bit(s) Value Description7

User’s Manual 837.3 Clock DoublerThe clock doubler is provided to allow a lower frequency crystal to be used for the main oscillator and to provide a

84 Rabbit 3000 MicroprocessorWhen the clock doubler is used and there is no subsequent division of the clock, the output clock will be asymmetric, as

User’s Manual 85variation in period on alternate clocks. This does not affect the no-wait states memory access time since two adjacent clocks are alwa

86 Rabbit 3000 Microprocessor7.4 Clock Spectrum SpreaderWhen enabled the spectrum spreader stretches and compresses the clocks in a complex pattern t

User’s Manual 877.5 Chip Select Options for Low PowerSome types of flash memory and RAM consume power whenever the chip select is enabled even if no

88 Rabbit 3000 MicroprocessorWhen operating in the 32 kHz mode, it is also possible to further divide the clock to a fre-quency as low as 2 kHz, furth

User’s Manual 89Figure 7-4. Short Chip Select Memory ReadFigure 7-5. Self-Timed Chip Select Memory Read CycleclockADDRDATAT1 T2ValidMEMOExBMEMCSxB32

90 Rabbit 3000 Microprocessor7.6 Output Pins CLK, STATUS, /WDTOUT, /BUFENCertain output pins can have alternate assignments as specified in Table 7-9